Accelerator-Rich, Heterogeneous Multi-Core Architectures

Project Overview

With architectural innovations and technology scaling reaching fundamental limits, energy efficiency is one of the primary design concerns today. It is well-accepted that specialization and heterogeneity can achieve both high performance and low power consumption, but there are fundamental tradeoffs between flexibility and specialization in determining the right mix of cores on a chip. Furthermore, with increasing acceleration, communication between heterogeneous components is rapidly becoming the major bottleneck, where architectural and runtime support for orchestration of data movement and optimized mapping of applications is critical. We study these questions through algorithm/architecture co-design of specialized architectures and accelerators for various domains, as well as novel architectures and tools for accelerator integration and heterogeneous system design.

Selected Publications

• Kishore Punniyamurthy and Andreas Gerstlauer, "TAFE: Thread Address Footprint Estimation for Capturing Data/Thread Locality in GPU Systems," Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), virtual conference, October 2020. [pdf]
• Kishore Punniyamurthy, Shomit Das, and Andreas Gerstlauer, "Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs," Proceedings of the IEEE International Conference on VLSI Design and Embedded Systems (VLSID), Bengaluru, India, January 2020. [pdf]
• Mochamad Asri, Dhairya Malhotra, Jiajun Wang, George Biros, Lizy K. John, and Andreas Gerstlauer, "Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods," IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 32, no. 8, pp. 2035-2048, February 2021. [pdf]
• Mochamad Asri, Curtis Dunham, Roxana Rusitoru, Andreas Gerstlauer, and Jonathan Beard, "The Non-Uniform Compute Device (NUCD) Architecture for Lightweight Accelerator Offload," Proceedings of the Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), Västerås, Sweden, March 2020. [pdf]
• Mochamad Asri, Ardavan Pedram, Lizy K. John, Andreas Gerstlauer, "Simulator Calibration for Accelerator-Rich Architecture Studies," Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, July 2016. [pdf]
• Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer, "A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores," Journal of Signal Processing Systems, Special Issue on Application Specific Processors and Architectures, vol. 77, no. 1-2, October 2014. [pdf]
• Ardavan Pedram, Andreas Gerstlauer, Robert van de Geijn, "Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator," IEEE Transactions on Computers (TC), Special Section on Computer Arithmetic, vol. 63, no. 8, August 2014. [pdf]
• Ardavan Pedram, Robert van de Geijn, Andreas Gerstlauer, "Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures ," IEEE Transactions on Computers (TC), Special Issue on Energy Efficient Computing, vol. 61, no. 12, December 2012. [pdf]

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