Accelerator-Rich, Heterogeneous Multi-Core Architectures

Project Overview

With architectural innovations and technology scaling reaching fundamental limits, energy efficiency is one of the primary design concerns today. It is well-accepted that specialization and heterogeneity can achieve both high performance and low power consumption, but there are fundamental tradeoffs between flexibility and specialization in determining the right mix of cores on a chip. Furthermore, with increasing acceleration, communication between heterogeneous components is rapidly becoming the major bottleneck, where architectural and runtime support for orchestration of data movement and optimized mapping of applications is critical. We study these questions through algorithm/architecture co-design of specialized architectures and accelerators for various domains, as well as novel architectures and tools for accelerator integration and heterogeneous system design.

Selected Publications


Mochamad Asri
Mochamad Asri
2020, Facebook (FRL), Menlo Park, CA
Kishore Punniyamurthy
2021, AMD Research, Austin, TX
Ardavan Pedram
2013, co-supervised with Prof. van de Geijn), post-doc at Stanford