Neuromorphic Computing System Co-Design

With the exponential growth in recent artificial intelligence (AI) complexity, the energy efficiency of computer systems has become a key concern. At the same time, the human brain can achieve similar or better performance than state-of-the-art AI systems with orders-of-magnitude less energy consumption. Neuromorphic computing applies brain-inspired concepts to hardware to achieve high levels of power efficiency. One promising subset of neuromorphic hardware focuses on the acceleration of spiking neural networks (SNNs), a type of artificial neural network that encodes information temporally as discrete spikes. SNN-based computation is naturally event-driven and sparse, enabling significant energy savings through asynchronous processing and fine-grained parallelization across distributed computing elements. While a range of efficient spiking digital and mixed-signal platforms have been implemented, the design-space is rapidly expanding. Recent neuromorphic research has proposed new devices, circuits, and algorithms that could lead to orders-of-magnitude improvement in power and performance over existing designs.

In this project, we explore how co-design across various levels can lead to improvements in power efficiency for SNN-based neuromorphic applications. Currently, a lack of tooling is limiting these co-design opportunities. In particular, modeling and simulation tools are crucial in supporting co-design efforts across the neuromorphic compute stack. At the device and circuit level, we are developing flexible machine learning-based surrogate modeling techniques for fast and accurate functional, power, and performance modeling of analog compute blocks. At the architectural level, we have developed a novel neuromorphic architecture simulator called SANA-FE (Simulating Advanced Neuromorphic Architectures for Fast Exploration). SANA-FE can rapidly predict the power performance of various architectures executing user-provided SNNs, including hybrid analog/digital designs that incorporate analog compute blocks for efficiency in an overall digital backend for scalability.